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// ============================================================================ // 模块: e203_clint_5stage // 功能: 五阶段中断控制器 优先级SEI>MEI>MTI>MSI 纯组合输出消除向量滞后 // ============================================================================ `include "e203_defines.v" module e203_clint_5stage ( input logic clk, rst_n, input logic msi, mti, mei, sei, input logic msie, mtie, meie, seie, input logic mstatus_mie, output logic irq, output logic [3:0] irq_id ); // 阶段1：中断源锁存（过滤未使能） reg msi_q, mti_q, mei_q, sei_q; always @(posedge clk or negedge rst_n) begin if (!rst_n) {msi_q, mti_q, mei_q, sei_q} <= '0; else begin msi_q <= msi & msie; mti_q <= mti & mtie; mei_q <= mei & meie; sei_q <= sei & seie; end end // 阶段2+3：优先级仲裁 (SEI > MEI > MTI > MSI) wire [3:0] pend = {sei_q, mei_q, mti_q, msi_q}; wire [3:0] grant; assign grant[3] = pend[3]; assign grant[2] = pend[2] & ~grant[3]; assign grant[1] = pend[1] & ~|grant[3:2]; assign grant[0] = pend[0] & ~|grant[3:1]; // 阶段4+5：组合输出（不寄存，与硬件状态同步） assign irq = |pend & mstatus_mie; assign irq_id = grant[3] ? 4'd11 : grant[2] ? 4'd8 : grant[1] ? 4'd7 : 4'd3; endmodule